1. Field of the Invention
The present invention relates generally to a signal generator and, more particularly, to a reference-signal generator suitable for use in a motor controlling system.
2. Description of the Prior Art
A motor controlling apparatus is known as shown in FIG. 6, in which a CPU 101 supplies a control signal, and a timer 102 generates a reference signal Fr from a clock signal CLK on the basis of the control signal from the CPU 101. The number of rotations of a motor 105 is detected by a rotation detector 106, and the frequency of the detector 106 output signal is divided by a frequency divider 108. A phase difference between the rotation number and the reference signal Fr is detected by a phase detector 103, and the output of the phase detector is used to form a phase loop. The output of the rotation detector 106 is also fed to a speed detecting unit 107 whose output is added to the output from the phase detector 103 by an adder 109, and the summed signals are amplified by an amplifier 104 before being fed to the motor 105. Thus, a speed loop is formed.
Such motor controlling apparatus controls the rotation rate of the motor by the speed loop and the phase loop, so as to synchronize the rotation with the reference signal Fr from the timer 102.
A reference-signal generating apparatus for generating a reference signal like that produced by the timer 102 is known to be constructed as shown in FIG. 7. The upper bits n1 and the lower bits n2 of the control signal from the CPU 101 are latched by a latch circuit 112 and repeatedly down-counted by a down counter 113 having the same number of counter steps as the bit number given by adding n1+n2. The frequency of an overflow output signal RIPPLE CLK thereof is divided by a frequency divider 114 formed of a flip-flop, so as to be one-half the frequency of the reference signal Fr.
In the above-described conventional motor controlling apparatus, when the motor rotation speed is controlled over a wide range, the reference signal Fr output from the timer 102 is also required to be varied over a wide range. Nevertheless, since the timer 102 repeatedly performs down-counting in response to speed data from the CPU 101 and outputs the reference signal Fr, a frequency ratio of a timer output when the speed data is N=99 to the timer output when the speed data being N=100, for example, is 1, while the frequency ratio of the timer output when the speed data is N=9 to the timer output when speed data is N=10 is 10.
Thus, the smaller the speed data from the CPU 101 becomes, the larger the rate of change of the reference signal Fr must become, so that a resolving power or resolution in the control of the motor speed is lowered. An increase of the resolving power of the timer 102 can be achieved by increasing the number of stages of the counter 113, however, in that case, in order to output the same reference signal Fr, the pulse rate of the input clock signal CLK 00 to the counter 113 is also required to be increased. Accordingly, there is then the inconvenience such that as the resolving power of the timer 102 is increased, a limitation of a maximum operation frequency of the counter 113 is caused and such limitation causes a limitation in the construction of the timer 102.